Static Analysis to Mitigate Soft Error Failures in Processors

By 2011, the Integrated Circuit(IC) feature sizes are expected to be reduced to 22nm from present day 45nm, and the soft error rate will increase by 3 to 4 orders of magnitude (from one per year to one per hour). International Technology Roadmap for Semiconductors(ITRS) indicates that techniques for mitigating soft errors are crucial for future generations of Integrated Circuits. Soft errors are transient faults, mostly caused by cosmic radiations and can lead to incorrect results or total system failure. While several process technology, circuit-level and microarchitectural techniques have been proposed to combat the challenge of soft errors, efficient soft error protection can be achieved at higher levels of design abstractions. Compiler solutions to mitigate failures due to soft errors are preferred since they do not require any design modification and are applicable on existing processors. However, the primary requirement for this is a technique to statically and quantitatively estimate of the impact of soft errors on a given program and this does not exist. The only known mechanisms to quantitatively estimate the impact of soft errors (vulnerability) is through simulation. Clearly simulation based approaches to estimate vulnerability are unusable for compiler transformations. This work presents the first static analysis to quantitatively estimate the vulnerability of programs to drive compiler optimizations. The static estimates, generated by the static analysis, are accurate to within 1 percentage error, and are able to drive code transformations to achieve significant reduction in vulnerability at minimal performance degradation.